Test circuit and semiconductor integrated circuit effectively carrying out verification of connection of nodes

ABSTRACT

A test circuit is incorporated in a device having an output circuit for outputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test output buffer connected in parallel with output nodes of the output circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the output nodes, and the test output buffer receives test data from the test data generating circuit and outputs the test data to the output nodes. Similarly, a test circuit is incorporated in a device having an input circuit for inputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test input buffer connected in parallel with input nodes of the input circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the input nodes, and the test input buffer receives test data from the test data generating circuit and inputs the test data to the input nodes.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a testing technique for testinga signal transmission system that carries out transmission and receptionof signals at high speed between LSI circuits (large-scale integratedcircuits) or between devices. More particularly, the present inventionrelates to a test circuit that carries out a verification of aconnection of nodes, and a semiconductor integrated circuit device towhich the test circuit is applied.

[0003] 2. Description of the Related Art

[0004] In recent years, there has been a remarkable improvement in theperformance of parts that constitute computers and other informationprocessing units. Along with this improvement, it has become necessaryto carry out transmission and reception of signals at high speed betweenLSIs (LSI chips) and between devices consisting of a plurality of LSIs.In other words, it has become necessary to carry out a high-speedtransmission of large-capacity signals between LSIs and between devicesconsisting of a plurality of LSIs. For example, in the solution servicefor network infrastructures, a high-speed transmission in the order ofgiga bits has become necessary, and a device called a “giga bit SERDES(Serializer and Deserializer)” has come to attract attention.

[0005] For a relatively low-speed data transmission in the order ofdozens of MHz, a single end transmission system (a system fortransmitting data using one signal line) like a TTL system hasconventionally been used. However, the single end transmission systemhas drawbacks in that the system easily receives external noise, andthat the transmission distance is short. Further, EMI (electromagneticinterface: electromagnetic radiation noise) occurs easily.

[0006] As the single end transmission system has the above problems,systems like the PCML (pseudo-current mode logic) system and the LVDS(low-voltage differential signaling) system that use differentialsignals (complementary signals) have come to be used fortransmission/reception terminals for high-speed data transmission. Thesesystems use two signal lines to transmit data using differential signalsof small amplitudes. It is possible to reduce EMI to about one fifth ofthat of the single end transmission system, and it is also possible tocancel noise between the two differential signal lines. Therefore, it ispossible to transmit data over a distance of dozens of meters. Further,as the differential signals have small amplitudes, it is possible torestrict crosstalk.

[0007] When a system including a transmitting/receiving circuit (anoutput circuit and an input circuit) for realizing a high-speedtransmission is considered, it is also necessary to pay attention to amethod of testing this system. In general, in order to confirm aconnection status of signals within a printed substrate, a JTAG(joint-test action group) test (a boundary scan test) is carried out. Inother words, in line with reduction in weight and sizes of electronicparts and progress of package techniques, an in-circuit test based onthe JTAG has been established as a standard technique.

[0008] The boundary scan is architecture for exchanging data with atarget semiconductor integrated circuit device (LSI). A mechanism forboundary scanning is built into the LSI. In other words, boundary scancells that perform operations equivalent to that of a test robe areprovided between the core and pins inside the LSI. These boundary scancells are connected to structure a shift register. A test (a keyboardtest or the like) is carried out based on the control of this shiftregister.

[0009] However, at present, there is no example of a JTAG test thattakes into account the differential terminals of the PCML system or theLVDS system, in the system built in with the transmitting/receivingcircuit. There has not yet been an established technique for inserting aBSR (boundary scan register) and a testing method. A test circuit like aBSR at a transmitter side is connected to an input stage of atransmitting circuit (output circuit), and test data is transmitted fromthe test circuit through the output circuit. In the mean time, a testcircuit at a receiver side is connected to an output stage of areceiving circuit (input circuit), and the test data is received throughthe input circuit.

[0010] As explained above, in order to carry out an operation test of anLSI chip or a test of connection between a package and a board on whichthe package is mounted (board test), it is necessary to carry out a testbased on a boundary scan. For confirming a connection between a systemincluding a transmitting/receiving circuit and an external circuit, itis inefficient to test a single end terminal and differential terminalsseparately.

[0011] When it is possible to carry out a JTAG test for differentialterminals in a similar manner to that for a single end terminal, itbecomes possible to perform the test in one pass. This can reduce testtime and improve the test efficiency. In this case, it is necessary thattest data is output from the output circuit to the transmitter terminal.On the other hand, it is necessary that the input circuit receives thetest data that is input from the receiving terminal.

[0012] However, when a signal processing circuit for carrying out ahigh-speed serial-to-parallel conversion, a transmitting circuit (outputcircuit) and a receiving circuit (input circuit) are connected together,the insertion of a test circuit like a BSR (boundary scan register) intobetween the transmitting circuit or the input circuit (receivingcircuit) and the signal processing circuit lowers the transmissionperformance. Further, in the case of a differential output and adifferential input, it is not possible to install a conventional BSR onthe terminal.

SUMMARY OF THE INVENTION

[0013] An object of the present invention is to provide a test circuitthat effectively carries out a verification of a connection of nodes,and a semiconductor integrated circuit device to which this test circuitis applied.

[0014] According to the present invention, there is provided a testcircuit that is incorporated in a device having an output circuit foroutputting a signal, and that carries out a verification of a connectionof nodes of the device, the test circuit comprising a test datagenerating circuit generating test data for carrying out a verificationof a connection of output nodes of the output circuit; and a test outputbuffer, connected in parallel with the output nodes, receiving test datafrom the test data generating circuit and outputting the test data tothe output nodes.

[0015] Further, according to the present invention, there is alsoprovided a semiconductor integrated circuit device having an outputcircuit transmitting a signal, and a test circuit carrying out averification of a connection of nodes, the test circuit comprising atest data generating circuit generating test data for carrying out averification of a connection of output nodes of the output circuit; anda test output buffer, connected in parallel with the output nodes,receiving test data from the test data generating circuit and outputtingthe test data to the output nodes.

[0016] The output circuit may output a differential signal, and the testoutput buffer may output the test data to the differential output nodes.The test circuit may carry out the verification of the connection of theoutput nodes in a differential signal status.

[0017] The test circuit may further comprise ESD protectors connectedbetween the output nodes and the test output buffers. When the outputcircuit has a function of converting parallel data into serial data, thetest data generating circuit may also have a function of convertingparallel data into serial data. The test data generating circuit may beconstructed of a circuit that has a register function capable ofperforming scanning. A test clock, which is different from an operationclock of the output circuit, may be supplied to the test data generatingcircuit. The test data generating circuit may output test data which isfixed to the verification of the connection of the output nodes.

[0018] An output of the output circuit may be provided with aterminating resistor. The test output buffer may directly control theoutput circuit. The test circuit may further comprise a test inputbuffer connected in parallel with input nodes of an input circuit towhich a signal is applied, and the test input buffer receiving test datathat are input to the input nodes. The test circuit may further compriseESD protectors connected between the input nodes and the test inputbuffers.

[0019] The input circuit may receive a differential signal, and the testinput buffer may receive test data that has been input to thedifferential input nodes. The test circuit may further comprise acircuit converting test data that has been input to the differentialinput nodes into a single end signal; and a test data processing circuitprocessing the test data. When the input circuit has a function ofconverting serial data into parallel data, the test data processingcircuit may also have a function of converting serial data into paralleldata.

[0020] The test data processing circuit may be constructed of a specificcircuit that has a register function capable of performing scanning. Thespecific circuit having the register function may have a test terminal.A test clock, which is different from an operation clock of the inputcircuit, may be supplied to the test data processing circuit. The testdata processing circuit may process test data which is fixed to theverification of the connection of the input nodes. The test circuit maycarry out a JTAG test of a device in which a single end terminal and adifferential terminal coexist.

[0021] Further, according to the present invention, there is provided atest circuit that is incorporated in a device having an input circuitfor inputting a signal, and that carries out a verification of aconnection of nodes of the device, the test circuit comprising a testdata generating circuit generating test data for carrying out averification of a connection of input nodes of the input circuit; and atest input buffer, connected in parallel with the input nodes, receivingtest data from the test data generating circuit and inputting the testdata to the input nodes.

[0022] In addition, according to the present invention, there is alsoprovided a semiconductor integrated circuit device having an inputcircuit transmitting a signal, and a test circuit carrying out averification of a connection of nodes, the test circuit comprising atest data generating circuit generating test data for carrying out averification of a connection of input nodes of the input circuit; and atest input buffer, connected in parallel with the input nodes, receivingtest data from the test data generating circuit and inputting the testdata to the input nodes.

[0023] The test circuit may further comprise ESD protectors connectedbetween the input nodes and the test input buffers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be more clearly understood from thedescription of the preferred embodiments as set forth below withreference to the accompanying drawings, wherein:

[0025]FIG. 1 is a block diagram showing one example of a semiconductorintegrated circuit device to which a test circuit relating to thepresent invention is applied;

[0026]FIG. 2 is a block diagram showing a first embodiment of a testcircuit relating to the present invention;

[0027]FIG. 3 is a block diagram showing a second embodiment of a testcircuit relating to the present invention;

[0028]FIG. 4 is a block diagram showing a third embodiment of a testcircuit relating to the present invention;

[0029]FIG. 5 is a block diagram showing a fourth embodiment of a testcircuit relating to the present invention;

[0030]FIG. 6 is a block diagram showing a fifth embodiment of a testcircuit relating to the present invention;

[0031]FIG. 7 is a block diagram showing a sixth embodiment of a testcircuit relating to the present invention;

[0032]FIG. 8 is a block diagram showing a seventh embodiment of a testcircuit relating to the present invention;

[0033]FIG. 9 is a block diagram showing an eighth embodiment of a testcircuit relating to the present invention;

[0034]FIG. 10 is a block circuit diagram showing a ninth embodiment of atest circuit relating to the present invention;

[0035]FIG. 11 is a block circuit diagram showing a tenth embodiment of atest circuit relating to the present invention;

[0036]FIG. 12 is a block circuit diagram showing an eleventh embodimentof a test circuit relating to the present invention;

[0037]FIG. 13 is a block circuit diagram showing a twelfth embodiment ofa test circuit relating to the present invention; and

[0038]FIG. 14 is a block circuit diagram showing a thirteenth embodimentof a test circuit relating to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Embodiments of a test circuit and a semiconductor integratedcircuit device relating to the present invention will be explained, indetail, with reference to the attached drawings.

[0040]FIG. 1 is a block circuit diagram showing one example of asemiconductor integrated circuit device to which a test circuit relatingto the present invention is applied. In FIG. 1, a reference number 1denotes a core (core logic), 2 denotes a differential input circuitsection (a receiving circuit macro), 3 denotes a differential outputcircuit section (a transmitting circuit macro), 4 denotes a single endsection, and 5 denotes a test control circuit.

[0041] The input circuit section 2 has input circuits (receivingcircuits) 20-0 to 20-18, each having a BSR (boundary scan register), towhich differential input signals AI0 to AI18 are input. A terminalRX-TDI (a TDI for the input circuit) of the input circuit section 2 isconnected to the test control circuit 5. A terminal RX-TDO (a TDO forthe input circuit) of the input circuit section 2 is connected to a BSR40-19 to which an input signal AI19 is input in the single end section4. The input circuits 20-0 to 20-18, each having a BSR, are insertedmanually. Embodiments of the input circuits 20-0 to 20-18, each having aBSR, will be explained in detail later with reference to the drawings(FIG. 6 to FIG. 10).

[0042] The output circuit section 3 has output circuits (transmittingcircuits) 31-0 to 31-18, each having a BSR, from which differentialoutput signals XO0 to XO18 are output. A terminal TX-TDO (a TDO for theoutput circuit) of the output circuit section 3 is connected to the testcontrol circuit 5. A terminal TX-TDI (a TDI for the output circuit) ofthe output circuit section 3 is connected to a BSR 41-19 from which anoutput signal XO19 is output in the single end section 4. The outputcircuits 31-0 to 31-18, each having a BSR, are inserted manually.Embodiments of the output circuits 31-0 to 31-18, each having a BSR,will be explained in detail later with reference to the drawings (FIG. 2to FIG. 5, and FIG. 11 to FIG. 14).

[0043] The single end section 4 has BSRs 40-19, 40-20, - - - to whichinput signals AI19, AI20, - - - of the single end are inputrespectively, and BSRs 41-19, 41-20, - - - from which output signalsXO19, XO20, - - - of the single end are output respectively. The BSRs ofthe single end section 4 are automatically inserted in a similar mannerto that of the conventional JTAG device.

[0044] The test control circuit (TAP controller) 5 is connected withterminals TDI, TMS, TCK, TRST, and TDO. In other words, like theconventional JTAG device, the semiconductor integrated circuit device(LSI) has the five terminals of the TDI, the TDO, the TMS, the TCK, andthe TRST, and one test mode terminal TEST-MODE. Access is made fromthese terminals to the test control circuit 5 that is built into thedevice. Test data are also input and output to/from these terminals.

[0045] The terminal TDI (test data input) is a serial test data inputterminal. Data or an instruction is input to this terminal TDI. When aninstruction has been input, this instruction is transferred to aninstruction register. When data has been input, this data is transferredto a data register.

[0046] The terminal TDO (test data output) is a serial test data outputterminal that bypasses the data input from the terminal TDI or thatsends out a value of the instruction register or the data register. Theterminal TMS (test mode select) and the terminal TCK (test clock) areterminals of signals for controlling the test control circuit 5incorporated in the JTAG device, and these realize a boundary scanarchitecture by controlling the data register, the instruction register,and a multiplexer.

[0047] The terminal TRST (test reset) is a terminal of a signal forinitializing the test control circuit 5. This terminal may be set as anoption.

[0048] As explained above, the semiconductor integrated circuit deviceshown in FIG. 1 provides a transmitting/receiving circuit macro havingBSRs mounted on the differential input terminals and differential outputterminals. It becomes possible to carry out a JTAG test at a systemlevel based on this transmitting/receiving circuit macro. In the case ofa single end signal (single signal), it is general that BSRs areautomatically inserted by using a test combining tool. However, it isnot possible to automatically insert in differential terminals by usingthis tool. It is necessary to manually insert BSRs for the differentialtransmitting terminals and differential receiving terminals. When theyare provided as a macro, and are built into a BSR chain of single endterminals that have been inserted automatically, it becomes possible tocarry out a JTAG test according to a single test control circuit. Basedon the JTAG test (boundary scan test), it is possible to confirm aconnection between circuit boards or between casings via a cable, forexample, as well as a connection on the board.

[0049]FIG. 2 is a block diagram showing a first embodiment of a testcircuit relating to the present invention. This shows an example of anoutput circuit (transmitting circuit). In FIG. 2 (and in FIG. 3 to FIG.5), a reference number 31 denotes an output circuit (corresponding toeach of the output circuits 31-0 to 31-18, each having a BSR, in FIG.1), 310 denotes a data output circuit, and 320 denotes a test dataoutput circuit. XO and /XO denote differential output terminals(corresponding to the XO0 to XO18 shown in FIG. 1).

[0050] As shown in FIG. 2, the output circuit 31 is constructed of adata output circuit 310, and a test data output circuit 320 that isconnected in parallel with this data output circuit 310. The data outputcircuit 310 has a signal processing circuit (output signal processingcircuit) 311, and a data output buffer 312. The test data output circuit320 has a test data generating circuit 321, and a test output buffer322.

[0051] Output data of the semiconductor integrated circuit device isoutput from the signal processing circuit 311 to the differential outputterminals XO and /XO via the differential data output buffer 312. Testdata is output from the test data generating circuit 321 to thedifferential output terminals XO and /XO via the test output buffer 322.

[0052] In other words, in the first embodiment, the test output buffer322 is connected to the output nodes (the differential output terminalsXO and /XO) of the data output buffer 312, in parallel with the dataoutput buffer 312.

[0053]FIG. 3 is a block diagram showing a second embodiment of a testcircuit relating to the present invention. In the second embodiment, adifferential test output buffer 322 is constructed of two buffers 3221and 3222, and an inverter 3223, as is clear from FIG. 3 in comparisonwith FIG. 2.

[0054] It is possible to arrange such that positive logic and negativelogic are generated for the output data of the test data generatingcircuit 321, and differential test data is output by using two buffersof positive and negative. When the test data generating circuit 321 isconstructed of a register that can perform scanning (scan register), itis possible to carry out boundary scanning at an external terminal ofthe semiconductor integrated circuit device (LSI chip).

[0055]FIG. 4 is a block diagram showing a third embodiment of a testcircuit relating to the present invention. In the third embodiment, ESD(electrostatic discharge) protectors 331 and 332 are inserted between adifferential test output buffer 322 and output nodes XO and /XOrespectively, as is clear from FIG. 4 in comparison with FIG. 2.

[0056] In the third embodiment, based on the provision of the ESDprotectors 331 and 332 between the differential test output buffer 322and the output nodes XO and /XO respectively, it becomes possible toimprove the ESD proof characteristics of the test circuit.

[0057]FIG. 5 is a block diagram showing a fourth embodiment of a testcircuit relating to the present invention.

[0058] As shown in FIG. 5, in the fourth embodiment, a signal processingcircuit 313 in a data output circuit 310 has a multiplexer function (n:1MUX) for converting n-bit parallel data into serial data. Further, atest data generating circuit 323 in a test data output circuit 320 alsogenerates test data in a sequence similar to that of the data outputcircuit 310.

[0059] When the test data generating circuit 323 (321) is constructed ofa register that can perform scanning, it is possible to carry outboundary scanning by bypassing the data output circuit 310. When a testclock is supplied to the test data generating circuit 323 (321),independently of the data output circuit 310, it is also possible tocarry out a test independently of the data output circuit 310.

[0060]FIG. 6 is a block diagram showing a fifth embodiment of a testcircuit relating to the present invention. This shows an example of aninput circuit (receiving circuit). In FIG. 6 (and in FIG. 7 to FIG. 9),a reference number 20 denotes an input circuit (corresponding to each ofthe input circuits 20-0 to 2018, each having a BSR, in FIG. 1), 210denotes a data input circuit, and 220 denotes a test data input circuit.AI and /AI denote differential input terminals (corresponding to the AI0to AI18 shown in FIG. 1).

[0061] As shown in FIG. 6, the input circuit 20 is constructed of a datainput circuit 210, and a test data input circuit 220 that is connectedin parallel with this input circuit 210. The data input circuit 210 hasa signal processing circuit (input signal processing circuit) 211, and adata input buffer 212. The test data input circuit 220 has a test dataprocessing circuit 221, and a test input buffer 222.

[0062] Data input from the differential input terminals AI and /AI ofthe semiconductor integrated circuit device are input to the signalprocessing circuit 211 via the data input buffer 212. Test data is inputto the test data processing circuit 221 via the test input buffer 222.

[0063] In other words, in the fifth embodiment, the test input buffer222 is connected to the input nodes (the differential input terminals AIand /AI) of the data input buffer 212, in parallel with the data inputbuffer 212.

[0064]FIG. 7 is a block diagram showing a sixth embodiment of a testcircuit relating to the present invention. In the sixth embodiment, oneof inputs (a positive input) of the differential test input buffer 222is connected to a positive input of the data input buffer 212. The otherinput (a negative input) of the differential test input buffer 222 isconnected to a reference voltage Vref, thereby to receive differentialtest data, as is clear from FIG. 7 in comparison with FIG. 6. When thetest data processing circuit 221 is constructed of a scan register, itis possible to carry out boundary scanning at an external terminal ofthe semiconductor integrated circuit device (LSI chip).

[0065]FIG. 8 is a block diagram showing a seventh embodiment of a testcircuit relating to the present invention. In the seventh embodiment,ESD protectors 231 and 232 are inserted into between input nodes AI and/AI and a test input buffer 222 respectively, as is clear from FIG. 8 incomparison with FIG. 6.

[0066] In the seventh embodiment, based on the provision of the ESDprotectors 231 and 232 between the input nodes AI and /AI and the testinput buffer 222, it becomes possible to improve the ESD proofcharacteristics in the test circuit.

[0067]FIG. 9 is a block diagram showing an eighth embodiment of a testcircuit relating to the present invention.

[0068] As shown in FIG. 9, in the eighth embodiment, a signal processingcircuit 213 in a data input circuit 210 has a demultiplexer function(n:1 DEMUX) for converting serial data into n-bit parallel data.Further, a test data processing circuit 223 in a test data input circuit220 also processes test data in a sequence similar to that of the datainput circuit 210.

[0069] When the test data processing circuit 223 (221) is constructed ofa register that can perform scanning, it is possible to carry outboundary scanning by bypassing the data input circuit 210. When a testclock is supplied to the test data processing circuit 223 (221)independent of the data input circuit 210, it is also possible to carryout a test independent of the data input circuit 210.

[0070]FIG. 10 is a block circuit diagram showing a ninth embodiment of atest circuit relating to the present invention. This shows a boundaryscan register (test data input circuit) 220 corresponding to adifferential input. In FIG. 10, a reference number 224 denotes adifferential sense amplifier (test input buffer), 225 denotes a testdata processing circuit, and 240 denotes a pass gate circuit.

[0071] As shown in FIG. 10, in the ninth embodiment, the test data inputcircuit 220 includes the differential sense amplifier 224, and the testdata processing circuit 225 that is constructed of a multiplexer 2251and a flip-flop 2252. The pass gate circuit 240 that is controlled basedon a test mode signal TEST-MODE is inserted into between differentialinput terminals AI and /AI and inputs of the differential senseamplifier 224. Reference symbols BSRI and /BSRI denote differentialboundary scan register input signals (input terminal: boundary scanregister input). The data input circuit 210 is constructed of a datainput buffer 212, and a signal processing circuit 213 that has ademultiplexer function.

[0072] The pass gate circuit 240 is constructed of two p-channel MOStransistors (pMOS transistors) 241 and 242, and an inverter 243, tocarry out ON/OFF control of the pMOS transistors (pass gates) 241 and242 according to the test mode signal TEST-MODE.

[0073] In the ninth embodiment, the differential sense amplifier (testinput buffer) 224 is controlled based on a test mode signal TEST-MODE(boundary scan test signal BSTEST). The test data input circuit 220 isinput with a test data input signal (TDI), a shift data register signal(SDR), and a capture data register signal (CDR), and outputs a test dataoutput signal (TDO).

[0074] In the ninth embodiment, the test data input circuit 220 iscompletely separated from the inside, and has a simple structure, inorder to provide a test circuit that is limited to the checking of aconnection with an external circuit.

[0075]FIG. 11 is a block circuit diagram showing a tenth embodiment of atest circuit relating to the present invention. This shows a boundaryscan register (test data output circuit) 320 corresponding to adifferential output. In FIG. 11, a reference number 324 denotes a senseamplifier (test output buffer), and 325 denotes a test data generatingcircuit.

[0076] In the tenth embodiment, the sense amplifier (test output buffer)324 for outputting a differential signal to the test data output circuit320 is provided, in order to make it possible to output a differentialoutput signal.

[0077] The test data generating circuit 325 is constructed of aninverter 3251, a latch 3252, and a flip-flop 3253. The data outputcircuit 310 is constructed of a signal processing circuit 313 that has amultiplexer function, a data output buffer 314, and an inverter 315.

[0078] The test output buffer 324 is supplied with a test mode signalTEST-MODE, and the data output buffer 314 is supplied with a test modesignal TEST-MODE of which the level has been inverted by the inverter315. Both the test output buffer 324 and the data output buffer 314 arecontrolled such that only one of these buffers becomes active, accordingto the test mode signal TEST-MODE. In other words, in order to avoidsuch a situation that the test data from the test data output circuit320 collides with the data from the data output circuit (driver) 310, itis controlled as follows. The test output buffer 324 and the data outputbuffer 314 are controlled such that only one of these buffers is turnedON based on the test mode signal TEST-MODE.

[0079] In the tenth embodiment, the test data generating circuit 325also receives a test data input signal (TDI), a capture data registersignal (CDR), and an update data register signal (UDR), and outputs atest data output signal (TDO).

[0080] In the tenth embodiment, the test data output circuit 320 iscompletely separated from the inside, and has a simple structure, inorder to provide a test circuit that is limited to the checking of aconnection with an external circuit.

[0081]FIG. 12 is a block circuit diagram showing an eleventh embodimentof a test circuit relating to the present invention. In FIG. 12, areference number 3140 denotes a driver (data output buffer), and 3160denotes a terminating resistor section.

[0082] The method of the tenth embodiment requires the use of atransistor having a large size, in order to increase the drivingcapacity of the output signal. This has a risk of reducing theperformance of high-speed data transfer due to the increased load. Toavoid this problem, in the eleventh embodiment, the inside of the dataoutput circuit 310 (the driver and the terminating resistor section) iscontrolled by using a single end signal SS as a signal from the testdata output circuit 320. Based on this, a differential signalcorresponding to the transmission data of the boundary scan register BSR(the output signal SS of the test data output circuit 320) is output tothe outside. In other words, according to the eleventh embodiment, it ispossible to prevent a reduction in the performance of high-speed datatransfer, as there is no influence from a load.

[0083] As shown in FIG. 12, in the eleventh embodiment, the test datagenerating circuit 326 (the test data output circuit 320) is constructedof an inverter 3261, a latch 3262, and a flip-flop 3263. The data outputcircuit 310 is constructed of a signal processing circuit 313 that has amultiplexer function, a driver (data output buffer) 3140, and aterminating resistor section 3160.

[0084] A single end output signal of the latch 3262 is supplied to thedriver 3140 to control this driver. Differential output terminals XO and/XO are provided with terminating resistors 3161 and 3162.

[0085]FIG. 13 is a block circuit diagram showing a twelfth embodiment ofa test circuit relating to the present invention. This shows one exampleof a detailed structure of the eleventh embodiment shown in FIG. 12.

[0086] As shown in FIG. 13, in the twelfth embodiment, a driver 3140 isconstructed of selectors 3141 and 3142, an inverter 3143, OR gates 3144to 3146, and output transistors (nMOS transistors) 3140 a and 3140 b. Areference symbol PDX denotes a power down signal. This signal is usuallyat a high level “H”, and becomes at a low level “L” when the power isdown. A test mode signal TEST-MODE is usually at a lower level “L”, andbecomes at a high level “H” in a test mode.

[0087] As shown in FIG. 13, in the twelfth embodiment, a terminatingresistor 3161 is constructed of pMOS transistors 31611 and 31612 thatare connected in parallel, and a terminating resistor 3162 isconstructed of pMOS transistors 31621 and 31622 that are connected inparallel. An output of the selector 3141 is supplied to a gate of thetransistor 31611, and an output of the selector 3142 is supplied to agate of the transistor 31621. One of the inputs (0 input) of theselectors 3141 and 3142 respectively is supplied with a power downsignal PDX. The other input (1 input) of the selector 3141 is suppliedwith a single end output signal SS of the test data output circuit 320(the test data generating circuit 326). The other input (1 input) of theselector 3142 is supplied with an output signal SS of the test dataoutput circuit 320 of which level has been inverted by the inverter3143. Both the selector 3141 and the selector 3142 are controlled basedon the test mode signal TEST-MODE.

[0088] When the test mode signal TEST-MODE is at the low level “L”(normal time), the gates of the transistors 31611 and 31621 are suppliedwith the power down signal PDX. These transistor 31611 and 31621 areboth OFF during a normal period, and they are both turned ON when thepower is down. During a test (during a JTAG test), the test mode signalTEST-MODE becomes at the high level “H”, and signals SS and /SS aresupplied to the gates of the transistors 31611 and 31621 respectively.One of the transistors 31611 and 31621 is turned ON and the other isturned OFF according to the single end output signal SS of the test dataoutput circuit 320 (the test data generating circuit 326).

[0089] A gate of the output transistor 3140 a is supplied with an outputof the OR gate 3145, and a gate of the output transistor 3140 b issupplied with an output of an OR gate 3146. The OR gate 3145 is suppliedwith an output signal DATA of positive logic of a pre-driver, and anoutput of the OR gate 3144. The OR gate 3146 is supplied with an outputsignal /DATA of negative logic of a pre-driver, and an output of the ORgate 3144. The OR gate 3144 is supplied with the test mode signalTEST-MODE to its positive logic input, and is supplied with the powerdown signal PDX to its negative logic input. Therefore, during a testmode (when the test mode signal TEST-MODE is at the high level “H”),both the output transistors 3140 a and 3140 b are fixed to ON. When thepower is down (when the power down signal PDX is at the low level “L”),both the output transistors 3140 a and 3140 b are also fixed to ON.

[0090] As explained above, according to the twelfth embodiment, theterminating resistors (pMOS transistors) 3161 and 3162 are controlledbased on the output signal of the test data output circuit 320 (thetransmission data of the boundary scan resistor BSR). A potentialdifference of the differential output terminals XO and /XO is adjustedbased on this control. As a result, in the twelfth embodiment, it ispossible to prevent a reduction in the performance of high-speed datatransmission without receiving the influence of load.

[0091]FIG. 14 is a block circuit diagram showing a thirteenth embodimentof a test circuit relating to the present invention. This shows anotherexample of a detailed structure of the eleventh embodiment shown in FIG.12.

[0092] As shown in FIG. 14, in the thirteenth embodiment, a driver 3140is constructed of selectors 3141 and 3142, an inverter 3143, outputresistors (nMOS transistors) 3140 a and 3140 b, OR gates 3151 and 3152,AND gates 3153 to 3156, and nMOS transistors 3157 and 3158.

[0093] According to the thirteenth embodiment, the output transistors3140 a and 3140 b that are fixed to ON during a test mode (when the testmode signal TEST-MODE is at the high level “H”) in the twelfthembodiment are fixed to OFF during the test mode. Further, in thethirteenth embodiment, the nMOS transistors 3157 and 3158 are providedcorresponding to differential output terminals XO and /XO respectively.These transistors 3157 and 3158 are controlled such that they are ONwhen pMOS transistors 31611 and 31621 of a terminating resistor section3160 are OFF respectively. A potential difference of the differentialoutput terminals XO and /XO is adjusted based on this control. As aresult, in the thirteenth embodiment, it is also possible to prevent areduction in the performance of high-speed data transmission withoutreceiving an influence of a load.

[0094] As explained in detail above, according to the present invention,it is possible to provide a test circuit capable of effectivelyperforming a verification of a connection of nodes between LSIs thathandle high-speed differential signals, and a semiconductor integratedcircuit device to which this test circuit is applied.

[0095] Many different embodiments of the present invention may beconstructed without departing from the spirit and scope of the presentinvention, and it should be understood that the present invention is notlimited to the specific embodiments described in this specification,except as defined in the appended claims.

What is claimed is:
 1. A test circuit that is incorporated in a devicehaving an output circuit for outputting a signal, and that carries out averification of a connection of nodes of said device, said test circuitcomprising: a test data generating circuit generating test data forcarrying out a verification of a connection of output nodes of saidoutput circuit; and a test output buffer, connected in parallel withsaid output nodes, receiving test data from said test data generatingcircuit and outputting the test data to said output nodes.
 2. The testcircuit as claimed in claim 1, wherein said output circuit outputs adifferential signal, and said test output buffer outputs said test datato said differential output nodes.
 3. The test circuit as claimed inclaim 2, wherein said test circuit carries out the verification of theconnection of said output nodes in a differential signal status.
 4. Thetest circuit as claimed in claim 1, further comprising ESD protectorsconnected between said output nodes and said test output buffers.
 5. Thetest circuit as claimed in claim 1 wherein, when said output circuit hasa function of converting parallel data into serial data, said test datagenerating circuit also has a function of converting parallel data intoserial data.
 6. The test circuit as claimed in claim 1, wherein saidtest data generating circuit is constructed of a circuit that has aregister function capable of performing scanning.
 7. The test circuit asclaimed in claim 1, wherein a test clock, which is different from anoperation clock of said output circuit, is supplied to said test datagenerating circuit.
 8. The test circuit as claimed in claim 1, whereinsaid test data generating circuit outputs test data which is fixed tothe verification of the connection of said output nodes.
 9. The testcircuit as claimed in claim 1, wherein an output of said output circuitis provided with a terminating resistor.
 10. The test circuit as claimedin claim 1, wherein said test output buffer directly controls saidoutput circuit.
 11. The test circuit as claimed in claim 1, furthercomprising a test input buffer connected in parallel with input nodes ofan input circuit to which a signal is applied, and said test inputbuffer receiving test data that are input to said input nodes.
 12. Thetest circuit as claimed in claim 1, further comprising ESD protectorsconnected between said input nodes and said test input buffers.
 13. Thetest circuit as claimed in claim 11, wherein said input circuit receivesa differential signal, and said test input buffer receives test datathat has been input to said differential input nodes.
 14. The testcircuit as claimed in claim 13, further comprising: a circuit convertingtest data that has been input to said differential input nodes into asingle end signal; and a test data processing circuit processing saidtest data.
 15. The test circuit as claimed in claim 14 wherein, whensaid input circuit has a function of converting serial data intoparallel data, said test data processing circuit also has a function ofconverting serial data into parallel data.
 16. The test circuit asclaimed in claim 14, wherein said test data processing circuit isconstructed of a specific circuit that has a register function capableof performing scanning.
 17. The test circuit as claimed in claim 16,wherein said specific circuit having said register function has a testterminal.
 18. The test circuit as claimed in claim 14, wherein a testclock, which is different from an operation clock of said input circuit,is supplied to said test data processing circuit.
 19. The test circuitas claimed in claim 14, wherein said test data processing circuitprocesses test data which is fixed to the verification of the connectionof said input nodes.
 20. The test circuit as claimed in claim 1, whereinsaid test circuit carries out a JTAG test of a device in which a singleend terminal and a differential terminal coexist.
 21. A semiconductorintegrated circuit device having an output circuit transmitting asignal, and a test circuit carrying out a verification of a connectionof nodes, said test circuit comprising: a test data generating circuitgenerating test data for carrying out a verification of a connection ofoutput nodes of said output circuit; and a test output buffer, connectedin parallel with said output nodes, receiving test data from said testdata generating circuit and outputting the test data to said outputnodes.
 22. The semiconductor integrated circuit device as claimed inclaim 21, wherein said output circuit outputs a differential signal, andsaid test output buffer outputs said test data to said differentialoutput nodes.
 23. The semiconductor integrated circuit device as claimedin claim 22, wherein said test circuit carries out the verification ofthe connection of said output nodes in a differential signal status. 24.The semiconductor integrated circuit device as claimed in claim 21,wherein said test circuit further comprises ESD protectors connectedbetween said output nodes and said test output buffers.
 25. Thesemiconductor integrated circuit device as claimed in claim 21 wherein,when said output circuit has a function of converting parallel data intoserial data, said test data generating circuit also has a function ofconverting parallel data into serial data.
 26. The semiconductorintegrated circuit device as claimed in claim 21, wherein said test datagenerating circuit is constructed of a circuit that has a registerfunction capable of performing scanning.
 27. The semiconductorintegrated circuit device as claimed in claim 21, wherein a test clock,which is different from an operation clock of said output circuit, issupplied to said test data generating circuit.
 28. The semiconductorintegrated circuit device as claimed in claim 21, wherein said test datagenerating circuit outputs test data which is fixed to the verificationof the connection of said output nodes.
 29. The semiconductor integratedcircuit device as claimed in claim 21, wherein an output of said outputcircuit is provided with a terminating resistor.
 30. The semiconductorintegrated circuit device as claimed in claim 21, wherein said testoutput buffer directly controls said output circuit.
 31. Thesemiconductor integrated circuit device as claimed in claim 21, whereinsaid test circuit further comprises a test input buffer connected inparallel with input nodes of an input circuit to which a signal isapplied, and said test input buffer receiving test data that are inputto said input nodes.
 32. The semiconductor integrated circuit device asclaimed in claim 21, wherein said test circuit further comprises ESDprotectors connected between said input nodes and said test inputbuffers.
 33. The semiconductor integrated circuit device as claimed inclaim 31, wherein said input circuit receives a differential signal, andsaid test input buffer receives test data that has been input to saiddifferential input nodes.
 34. The semiconductor integrated circuitdevice as claimed in claim 33, wherein said test circuit furthercomprises: a circuit converting test data that has been input to saiddifferential input nodes into a single end signal; and a test dataprocessing circuit processing said test data.
 35. The semiconductorintegrated circuit device as claimed in claim 34 wherein, when saidinput circuit has a function of converting serial data into paralleldata, said test data processing circuit also has a function ofconverting serial data into parallel data.
 36. The semiconductorintegrated circuit device as claimed in claim 34, wherein said test dataprocessing circuit is constructed of a specific circuit that has aregister function capable of performing scanning.
 37. The semiconductorintegrated circuit device as claimed in claim 36, wherein said specificcircuit having said register function has a test terminal.
 38. Thesemiconductor integrated circuit device as claimed in claim 34, whereina test clock, which is different from an operation clock of said inputcircuit, is supplied to said test data processing circuit.
 39. Thesemiconductor integrated circuit device as claimed in claim 34, whereinsaid test data processing circuit processes test data which is fixed tothe verification of the connection of said input nodes.
 40. Thesemiconductor integrated circuit device as claimed in claim 21, whereinsaid test circuit carries out a JTAG test of a device in which a singleend terminal and a differential terminal coexist.
 41. A test circuitthat is incorporated in a device having an input circuit for inputting asignal, and that carries out a verification of a connection of nodes ofsaid device, said test circuit comprising: a test data generatingcircuit generating test data for carrying out a verification of aconnection of input nodes of said input circuit; and a test inputbuffer, connected in parallel with said input nodes, receiving test datafrom said test data generating circuit and inputting the test data tosaid input nodes.
 42. The test circuit as claimed in claim 41, furthercomprising ESD protectors connected between said input nodes and saidtest input buffers.
 43. A semiconductor integrated circuit device havingan input circuit transmitting a signal, and a test circuit carrying outa verification of a connection of nodes, said test circuit comprising: atest data generating circuit generating test data for carrying out averification of a connection of input nodes of said input circuit; and atest input buffer, connected in parallel with said input nodes,receiving test data from said test data generating circuit and inputtingthe test data to said input nodes.
 44. The semiconductor integratedcircuit device as claimed in claim 43, wherein said test circuit furthercomprises ESD protectors connected between said input nodes and saidtest input buffers.